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128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer

Shenzhen Saef Technology Ltd.
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    Buy cheap 128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer from wholesalers
     
    Buy cheap 128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer from wholesalers
    • Buy cheap 128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer from wholesalers
    • Buy cheap 128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer from wholesalers

    128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer

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    Brand Name : SAEF
    Model Number : SFBM12864YB057A
    Certification : ISO9001 / ISO14000
    Price : Negotiable based on order lot quantity
    Payment Terms : L/C, , T/T, Western Union
    Supply Ability : 3000K pcs per month
    Delivery Time : 1-5 weeks
    • Product Details
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    128x64 FSTN Graphic LCD Display Positive LCD 12864 Dots LCD Manufacturer

    Features


    • Dot Matrix: 128×64 Dots
    • LCD Mode: FSTN/NEGATIVE/TRANSFLECTIVE
    • Controller IC:ST7565
    • Driving Method: 1/65 Duty; 1/9 Bias
    • Viewing Angie: 6 O’clock direction
    • Interface: 6800-Series OR 8080 Series MPU
    • Operating voltage: 3.0V
    • Operating Temperature Range: -20 to +70℃
    • Storage Temperature Range : -30 to +80℃
    • Backlight Speciality : Led(3PCS) Vf=3.0±0.2V ,IF=45MA

    Mechanical Specifications


    ITEMSPECIFICATIONSUNIT
    Module Size(L×W×H)40.0L×28.0.0W×4.5(max)Hmm
    View Area(W×H)37.0×20.0mm
    Effective Area128×64dot
    Dot Pitch(W×H)0.27×0.27mm
    Dot Size(W×H)0.245×0.245mm

    Drawing



    Pin Definition


    ITEMSYMBOLLEVELFUNCTION
    1VDD+3.3VPower Supply For Logic
    2C86H/LH:6800 Parallel L:8080 Parallel
    3VSS0VPower Ground
    4V0

    Connect a capacitor between this terminal and the VSS terminal

    5V1
    6V2
    7V3
    8V4
    9CAP2-Connect a capacitor between this terminal and the CAP2+ terminal
    10CAP2+Connect a capacitor between this terminal and the CAP2- terminal
    11CAP1-Connect a capacitor between this terminal and the CAP1- terminal
    12CAP1+Connect a capacitor between this terminal and the CAP1+ terminal
    13CAP3+Connect a capacitor between this terminal and the CAP1- terminal
    14VOUTConnect a capacitor between this terminal and the VSS or VDD terminal
    15VSS0VPower Ground

    16

    ~

    23


    D7~D0


    H/L


    8-bit bi-directional data bus


    24


    /RD


    H/L

    8080 Parallel:The data bus is in an output status when this signal is “L ”.

    6800 Paralle:This is the enable clock input terminal of the 6800 Series MPU.


    25


    /WR


    H/L

    8080 Parallel:The signals on the data bus are latched at the rising edge of the /WR signal.

    6800 Paralle:H:Read L:Write

    26A0H/L

    H:Indicates that D0 to D7 are display data.

    L:Indicates that D0 to D7 are control data.

    27/RESH/LThe reset operation is performed by the /RES signal level
    28CS1LChip select signal

    Display Data RAM (DDRAM)


    The Display Data RAM stores pixel data for the LCD. It is 64-row by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 64 rows are divided into 8 pages (Page 0~Page 7) of 8lines . Data is written to the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor correspond to the LCD common lines. The LCD controller and MPU interface operate independently, data can be written into RAM at the same time when data is being displayed without flicker on LCD.


    Page Address Circuit


    This circuit is for providing a Page Address to Display Data RAM. It incorporates 4-bit Page Address register changed by only the “Set Page Address” instruction. The Page Address must be set before accessing DDRAM content. Page Address “8” is a special RAM area for the icons and display data D0 is only valid.


    Column Address Circuit


    Column Address Circuit has a 8-bit preset counter that provides Column Address to the Display Data RAM (DDRAM). The DDRAM column address is specified by the“Set Column Address ” command. The specified column address is incremented (+1) with each display data read/write access. This allows the MPU display data to be accessed continuously. Control flag MY can invert the output order of the COM pads. And the MX flag makes it possible to invert the relationship between the Column Address and the SEG outputs. It is necessary to rewrite the display data into DDRAM after changing MX flag setting. Please refer to ST7565 datasheet.


    Facilities and Certification


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